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ST93C46A,46c,46t st93c47c,47t 1k (64 x 16 or 128 x 8) serial microwire eeprom not for new design june 1997 1/13 this is information on a product still in production bu t not recommended for new de signs. ai00871c d v cc st93c46 st93c47 v ss c q s org figure 1. logic diagram 1 million erase/write cycles, with 40 years data retention dual organization: 64 x 16 or 128 x 8 byte/word and entire memory programming instructions self-timed programming cycle with auto-erase ready/busy signal during programming single supply voltage: 4.5v to 5.5v for st93c46 version 3v to 5.5v for st93c47 version sequential read operation 5ms typical programming time enhanced esd/latch up performance for oco version ST93C46A, st93c46c, st93c46t, st93c47c, st93c47t are replaced by the m93c46 description this specification covers a range of 1k bit serial eeprom products, the ST93C46A,46c,46t specified at 5v 10% and the st93c47c,47t specified at 3v to 5.5v. in the text, products are referred to as st93c46. the st93c46 is a 1k bit electrically erasable programmable memory (eeprom) fabricated with sgs-thomson's high endurancesingle polysili- con cmos technology. the memory is accessed through a serial input (d) and output (q). s chip select input d serial data input q serial data output c serial clock org organisation select v cc supply voltage v ss ground table 1. signal names 8 1 so8 (m) 150mil width 8 1 psdip8 (b) 0.4mm frame
symbol parameter value unit t a ambient operating temperature 40 to 125 c t stg storage temperature 65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v io input or output voltages (q = v oh or hi-z) 0.3 to v cc +0.5 v v cc supply voltage 0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (2) ST93C46A,t st93c46c 2000 4000 v electrostatic discharge voltage (machine model) (3) st93c46 500 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the sgs-thomson sure program and other relevant quality documents. 2. mil-std-883c, 3015.7 (100pf, 1500 w ). 3. eiaj ic-121 (condition c) (200pf, 0 w ). table 2. absolute maximum ratings (1) 1 v ss q org du c sv cc d ai00874c st93c46 st93c47 2 3 4 8 7 6 5 figure 2b. so pin connections warning: du = don't use v ss q org du c sv cc d ai00872c st93c46 st93c47 1 2 3 4 8 7 6 5 figure 2a. dip pin connections warning: du = don't use 1 d c q v ss v cc du org s ai00982b st93c46t st93c47t 2 3 4 8 7 6 5 figure 2c. so, 90 turn, pin connections warning: du = don't use the 1k bit memory is divided into either 128 x 8 bit bytes or 64 x 16 bit words. the organization may be selected by a signal on the org input. the memory is accessed by a set of instructions which includes read a byte/word, write a byte/word, erase a byte/word, erase all and write all. a read instruction loads the address of the first byte/word to be read into an internal address pointer. the data is then clocked out serially. the address pointer is automatically incremented after the data is output and, if the chip select input (s) is held high, the st93c46 can output a sequen- tial stream of data bytes/words. in this way, the memory can be read as a data stream from 8 to 1024 bits long, or continuously as the address description (cont'd) 2/13 ST93C46A/46c/46t, st93c47c/47t
input rise and fall times 20ns input pulse voltages 0.4v to 2.4v input timing reference voltages 1v to 2.0v output timing reference voltages 0.8v to 2.0v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai00815 2.4v 0.4v 2.0v 0.8v 2v 1v input output figure 3. ac testing input output waveforms symbol parameter test condition min max unit c in input capacitance v in =0v 5 pf c out output capacitance v out =0v 5 pf note: 1. sampled only, not 100% tested. table 3. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 2.5 m a i lo output leakage current 0v v out v cc , q in hi-z 2.5 m a i cc supply current (ttl inputs) s = v ih , f = 1 mhz 3 ma supply current (cmos inputs) s = v ih , f = 1 mhz 2 ma i cc1 supply current (standby) s=v ss ,c=v ss , org = v ss or v cc 50 m a v il input low voltage (d, c, s) v cc =5v 10% 0.3 0.8 v 3v v cc 4.5v 0.3 0.2 v cc v v ih input high voltage (d, c, s) v cc =5v 10% 2 v cc +1 v 3v v cc 4.5v 0.8 v cc v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v i ol =10 m a 0.2 v v oh output high voltage i oh = 400 m a 2.4 v i oh = 10 m av cc 0.2 v table 4. dc characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v or 3v to 5.5v) 3/13 ST93C46A/46c/46t, st93c47c/47t
symbol alt parameter test condition min max unit t shch t css chip select high to clock high 50 ns t clsh t sks clock low to chip select high 100 ns t dvch t dis input valid to clock high 100 ns t chdx t dih clock high to input transition temp. range: grade 1 100 ns temp. range: grades 3, 6 200 ns t chql t pd0 clock high to output low 500 ns t chqv t pd1 clock high to output valid 500 ns t clsl t csh clock low to chip select low 0 ns t slch chip select low to clock high 250 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 500 ns t slqz t df chip select low to output hi-z ST93C46A 300 ns st93c46c, 47c 200 ns t chcl t skh clock high to clock low note 2 250 ns t clch t skl clock low to clock high note 2 250 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency 0 1 mhz notes: 1. chip select must be brought low for a minimum of 250 ns (t slsh ) between consecutive instruction cycles. 2. the clock frequency specification calls for a minimum clock period of 1 m s, therefore the sum of the timings t chcl +t clch must be greater or equal to 1 m s. for example, if t chcl is 250 ns, then t clch must be at least 750 ns. table 5. ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v or 3v to 5.5v) ai01428 c op code op code start s d op code input start tdvch tshch tclsh tchcl tclch tchdx figure 4. synchronous timing, start and op-code input 4/13 ST93C46A/46c/46t, st93c47c/47t
figure 5. synchronous timing, read or write ai00820c c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15/q7 q0 ai01429 c d q address/data input hi-z tdvch tslch a0/d0 s write cycle tslsh tchdx an tclsl tslqz busy tshqv tw ready counter automatically rolls over to '00' when the highest address is reached. programming is internally self-timed (the external clock signal on c input may be disconnected or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruc- tion. the write instruction writes 8 or 16 bits at one time into one of the 128 bytes or 64 words. after the start of the programming cycle a busy/ready signal is available on the data output (q) when chip select (s) is high. an internal feature of the st93c46 provides power-on data protection by inhibiting any opera- tion when the supply is too low. the design of the st93c46 and the high endurance cmos technol- ogy used for its fabrication give an erase/write cycle endurance of 1,000,000 cycles and a data retention of 40 years. the du (don't use) pin does not affect the function of the memory and it is reserved for use by sgs- thomson during test sequences.the pin may be left unconnected or may be connected to v cc or v ss . direct connection of du to v ss is recom- mended for the lowest standby power consump- tion. description (cont'd) 5/13 ST93C46A/46c/46t, st93c47c/47t
memory organization the st93c46 is organised as 128 bytes x 8 bits or 64 words x 16 bits. if the org input is left uncon- nected (or connected to v cc ) the x16 organization is selected, when org is connected to ground (v ss ) the x8 organization is selected. when the st93c46 is in standby mode, the org input should be unconnected or set to either v ss or v cc in order to get minimum power consumption. any voltage between v ss and v cc applied to org may increase the standby current value. power-on data protection during power-up, a power on reset sequence is run in order to reset all internal programming cir- cuitry and the device is set in the write disable mode. when v cc reaches its functional value, the device is properlyreset (in the write disable mode) and is ready to decode and execute an incoming instruction. instructions the st93c46 has seven instructions, as shown in table 6. each instruction is preceded by the rising edge of the signal applied on the s input (assuming that the clock c is low), followed by a '1' read on d input during the rising edge of the clock c. the op-codes of the instructions are made up of the 2 followingbits. some instructions useonly these first two bits, others use also the first two bits of the address to define the op-code. the op-code is followed by an address for the byte/word which is made up of six bits for the x16 organization or seven bits for the x8 organization. the st93c46 is fabricated in cmos technology and is therefore able to run from zero hz (static input signals) up to the maximum ratings (specified in table 5). read the read instruction (read) outputs serial data on the data output (q). when a read instruction is received, the instruction and address are de- coded and the data from the memory is transferred into an output shiftregister. a dummy '0' bit is output first followed by the 8 bit byte or the 16 bit word with the msb first. output data changes are triggered by the low to high transition of the clock (c). the st93c46 will automatically increment the address and will clock out the next byte/word as long as the chip select input (s) is held high. in this case the dummy '0' bit is not output between bytes/words and a continuous stream of data can be read. erase/write enable and disable the erase/write enable instruction (ewen) authorizesthe following erase/write instructions to be executed, the erase/write disable instruction (ewds) freezes the execution of the following erase/write instructions. when power is first ap- plied to the st93c46, erase/write is inhibited. when the ewen instruction is executed, write instructions remain enabled until an erase/write disable instruction (ewds) is executed or v cc falls below the power-on reset threshold. to protect the memory contents from accidental corruption, it is advisable to issue the ewds instruction after every write cycle. the read instruction is not affected by the ewen or ewds instructions. instruction description op-code x8 org address (org = 0) data x16 org address (org = 1) data read read data from memory 10 a6-a0 q7-q0 a5-a0 q15-q0 write write data to memory 01 a6-a0 d7-d0 a5-a0 d15-d0 ewen erase/write enable 00 11xxxxx 11xxxx ewds erase/write disable 00 00xxxxx 00xxxx erase erase byte or word 11 a6-a0 a5-a0 eral erase all memory 00 10xxxxx 10xxxx wral write all memory with same data 00 01xxxxx d7-d0 01xxxx d15-d0 note: x = don't care bit. table 6. instruction set 6/13 ST93C46A/46c/46t, st93c47c/47t
ai00878c 110 an a0 qn q0 data out d s q read s write addr op code 1 0 an a0 data in d q op code dn d0 1 busy ready s erase write enable 1 0 xn x0 d op code 1 01 s erase write disable 1 0 xn x0 d op code 00 0 check status addr figure 6. read, write, ewen, ewds sequences erase the erase instruction (erase) programs the ad- dressed memory byte or word bits to '1'. once the address is correctly decoded,the falling edge of the chip select input (s) starts a self-timed program- ming cycle. if the st93c46 is still performing the write cycle, the busy signal (q = 0) will be returned if s is driven high, and the st93c46 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the st93c46 is ready to receive a new instruction. write the write instruction (write) is followed by the address and the 8 or 16 data bits to be written. data input is sampled on the low to high transition of the clock. after the last data bit has been sampled, chip select (s) must be brought low before the next rising edge of the clock (c), in order to start the self-timed programming cycle. if the st93c46 is still performing the write cycle, the busy signal notes: 1. an: n = 5 for x16 org. and 6 for x8 org. 2. xn: n = 3 for x16 org. and 4 for x8 org. 7/13 ST93C46A/46c/46t, st93c47c/47t
ai00879b s erase 11 d q addr op code 1 busy ready check status s erase all 10 d q op code 1 busy ready check status 00 an a0 xn x0 addr figure 7. erase, eral sequences (q = 0) will be returned if s is driven high, and the st93c46 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the st93c46 is ready to receive a new instruction. the write instruction includes an automatic erase cycle before writing the data, it is therefore unnec- essary to execute an erase instruction before a write instruction execution. erase all the erase all instruction (eral) erases the whole memory (all memory bits are set to o1o). a dummy address is input during the instruction transfer and the erase is made in the same way as the erase instruction above. if the st93c46 is still performing the write cycle, the busy signal (q = 0) will be returned if s is driven high, and the st93c46 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the st93c46 is ready to receive a new instruction. write all for correct operation, an eral instruction should be executed before the wral instruction. the write all instruction (wral) writes the data input byte or word to all the addresses of the memory. in the wral instruction, no automatic erase is made so all bytes/words must be erased before the wral instruction. if the st93c46 is still performing the write cycle, the busy signal (q = 0) will be returned if s is driven high, and the st93c46 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the st93c46 is ready to receive a new instruction. notes: 1. an: n = 5 for x16 org. and 6 for x8 org. 2. xn: n = 3 for x16 org. and 4 for x8 org. instructions (cont'd) 8/13 ST93C46A/46c/46t, st93c47c/47t
ready/busy status during every programming cycle (after a write, erase, wral or eral instruction) the data out- put (q) indicates the ready/busy status of the memory when the chip select is driven high. once the st93c46 is ready, the data output is set to '1' until a new start bit is decoded or the chip select is brought low. common i/o operation the data output (q) and data input (d) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (a0) and the first data bit output by q. the reader should refer to the sgs-thomson application note omicrowire eeprom common i/o opera- tiono. differences between ST93C46A and st93c46c the st93c46c is an enhanced version of the ST93C46A and offers the following extra features: enhanced esd voltage functional security filtering glitches on the clock input (c). refer to table 2 (absolute maximum ratings) for more about esd limits. the following description will detail the clock pulses counter (available only on the st93c46c). in a normal environment, the st93c46 is expected to receive the exact amount of data on the d input, that is the exact amount of clock pulses on the c input. in a noisy environment, the amount of pulses re- ceived (on the clock input c) may be greater than the clock pulsesdelivered by the master (microcon- troller) driving the st93c46c. in such a case, a part of the instruction is delayed by one bit (see figure 9), and it may induce an erroneous write of data at a wrong address. the st93c46c has an on-board counter which counts the clock pulses from the start bit until the falling edge of the chip select signal. for the write instructions, the number of clock pulses incoming to the counter must be exactly 18 (with the organisation by 8) from the start bit to the falling edge of chip select signal (1 start bit + 2 bits of op-code + 7 bits of address + 8 bits of data = 18): if so, the st93c46c executes the write instruction; if the number of clock pulses is not equal to 18, the instruction will not be executed (and data will not be corrupted). in the same way, when the organisation by 16 is selected, the number of clock pulses incoming to the counter must be exactly 25 (1 start bit + 2 bits of op-code + 6 bits of address + 16 bits of data = 25) from the start bit to the falling edge of chip select signal: if so, the st93c46c executes the write instruction; if the number of clock pulses is not equal to 25, the instruction will not be executed (and data will not be corrupted). the clock pulse counter is active only on erase and write in- structions (write, erase, eral, wrall). ai00880c s write all data in d q addr op code dn d0 busy ready check status 100 0 1 xn x0 figure 8. wral sequence note: 1. xn: n = 3 for x16 org. and 4 for x8 org. 9/13 ST93C46A/46c/46t, st93c47c/47t
ordering information scheme operating voltage 46 4.5v to 5.5v 47 3v to 5.5v revision a (1) cmos f3 c cmos f4 t cmos f3 90 turn pin out package b (2) psdip8 0.4 mm frame m so8 150mil width temperature range 1 0 to 70 c 6 40 to 85 c 3 (3) 40 to 125 c option 013tr tape & reel packing (a, t ver.) tr tape & reel packing (c version) example: ST93C46A m 1 013tr notes: 1. revision oao is not available for the st93c47 product. 2. st93c46cb1 is available in 0.25mm lead frame only. 3. temperature range on special request only. devices are shipped from the factory with the memory content set at all o1'so (ffffh for x16, ffh for x8). for a list of available options (operating voltage, package, etc...) or for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. ai01395 s an-1 c d write start d0 o1o o0o an glitch an-2 address and data are shifted by one bit figure 9. write sequence with one clock glitch 10/13 ST93C46A/46c/46t, st93c47c/47t
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 4.80 0.189 a1 0.70 0.028 a2 3.10 3.60 0.122 0.142 b 0.38 0.58 0.015 0.023 b1 1.15 1.65 0.045 0.065 c 0.38 0.52 0.015 0.020 d 9.20 9.90 0.362 0.390 e 7.62 0.300 e1 6.30 7.10 0.248 0.280 e1 2.54 0.100 ea 8.40 0.331 eb 9.20 0.362 l 3.00 3.80 0.118 0.150 n8 8 cp 0.10 0.004 psdip8 drawing is not to scale psdip8 - 8 pin plastic skinny dip, 0.4mm lead frame 11/13 ST93C46A/46c/46t, st93c47c/47t
so-a e n cp b e a d c l a1 a 1 h hx45 symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 so8 drawing is not to scale so8 - 8 lead plastic small outline, 150 mils body width 12/13 ST93C46A/46c/46t, st93c47c/47t
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved ? microwire is a registered trademark of national semiconductor corp. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 13/13 ST93C46A/46c/46t, st93c47c/47t

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